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WV3HG64M64EEU-D4
ADVANCED*
512MB - 64Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM
FEATURES
Unbuffered 200-pin, Small-Outline DIMM (SODIMM) Fast data transfer rates: PC2-5300*, PC2-4200 and PC2-3200 Utilizes 667*, 533 and 400 MT/s DDR2 SDRAM components VCC = 1.8V 0.1V VCCSPD = 1.7V to 3.6V JEDEC standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option Four-bit prefetch architecture DLL to align DQ and DQS transitions with CK Multiple internal device banks for concurrent operation Supports duplicate output strobe (RDQS/RDQS#) Programmable CAS# latency (CL): 3, 4, and 5* Adjustable data-output drive strength On-die termination (ODT) Serial Presence Detect (SPD) with EEPROM Auto & self refresh (64ms: 8,192 cycle refresh) Gold edge contacts RoHS Compliant JEDEC Package option * 200 Pin (SO-DIMM) * PCB - 30.00mm (1.181") TYP.
NOTE: Consult factory for availability of: * Vendor source control options * Industrial temperature option
DESCRIPTION
The WV3HG64M64EEU is a 64Mx64 Double Data Rate 2 SDRAM memory module based on 512Mb DDR2 SDRAM components. The module consists of eight 64Mx8, in FBGA package mounted on a 200 pin SO-DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to change or cancellation without notice.
OPERATING FREQUENCIES
PC2-5300* Clock Speed CL-tRCD-tRP
Note: * Consult factory for availability
PC2-4200 266MHz 4-4-4
PC2-3200 200MHz 3-3-3
333MHz 5-5-5
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PIN CONFIGURATION
PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL 51 DQS2 101 A1 151 DQ42 1 VREF 2 VSS 52 DM2 102 A0 152 DQ46 53 VSS 103 153 DQ43 3 VSS VCC 4 DQ4 54 VSS 104 154 DQ47 VCC 5 DQ0 55 DQ18 105 A10/AP 155 VSS 6 DQ5 56 DQ22 106 BA1 156 VSS 7 DQ1 57 DQ19 107 BA0 157 DQ48 8 VSS 58 DQ23 108 RAS# 158 DQ52 9 VSS 59 VSS 109 WE# 159 DQ49 10 DM0 60 VSS 110 CS0# 160 DQ53 11 DQS0# 61 DQ24 111 161 VSS VCC 12 VSS 62 DQ28 112 162 VSS VCC 13 DQS0 63 DQ25 113 CAS# 163 NC 14 DQ6 64 DQ29 114 ODT0 164 CK1 65 VSS 115 NC 165 VSS 15 VSS 16 DQ7 66 VSS 116 A13 166 CK1# 17 DQ2 67 DM3 117 167 DQS6# VCC 18 VSS 68 DQS3# 118 168 VSS VCC 19 DQ3 69 NC 119 NC 169 DQS6 20 DQ12 70 DQS3 120 NC 170 DM6 21 VSS 71 VSS 121 VSS 171 VSS 22 DQ13 72 VSS 122 VSS 172 VSS 23 DQ8 73 DQ26 123 DQ32 173 DQ50 74 DQ30 124 DQ36 174 DQ54 24 VSS 25 DQ9 75 DQ27 125 DQ33 175 DQ51 26 DM1 76 DQ31 126 DQ37 176 DQ55 27 VSS 77 VSS 127 VSS 177 VSS 28 VSS 78 VSS 128 VSS 178 VSS 29 DQS1# 79 CKE0 129 DQS4# 179 DQ56 30 CK0 80 NC 130 DM4 180 DQ60 31 DQS1 81 131 DQS4 181 DQ57 VCC 32 CK0# 82 132 VSS 182 DQ61 VCC 83 NC 133 VSS 183 VSS 33 VSS 34 VSS 84 NC 134 DQ38 184 VSS 35 DQ10 85 NC 135 DQ34 185 DM7 36 DQ14 86 NC 136 DQ39 186 DQS7# 137 DQ35 187 VSS 37 DQ11 87 VCC 38 DQ15 88 138 VSS 188 DQS7 VCC 39 VSS 89 A12 139 VSS 189 DQ58 40 VSS 90 A11 140 DQ44 190 VSS 41 VSS 91 A9 141 DQ40 191 DQ59 42 VSS 92 A7 142 DQ45 192 DQ62 43 DQ16 93 A8 143 DQ41 193 VSS 44 DQ20 94 A6 144 VSS 194 DQ63 45 DQ17 95 145 VSS 195 SDA VCC 46 DQ21 96 146 DQS5# 196 VSS VCC 47 VSS 97 A5 147 DM5 197 SCL 48 VSS 98 A4 148 DQS5 198 SA0 49 DQS2# 99 A3 149 VSS 199 VCCSPD 50 NC 100 A2 150 VSS 200 SA1
WV3HG64M64EEU-D4
ADVANCED
PIN NAMES
SYMBOL A0-A13 ODT0 CK0, CK0# CK1, CK1# CKE0 CS0# RAS#, CAS#, WE# BA0, BA1 DM0-DM7 DQ0-DQ63 DQS0-DQS7 DQS0#-DQS7# SCL SA0-SA1 SDA VCC VREF VSS VCCSPD NC DESCRIPTION Address input On-Die Termination Differential Clock Inputs Differential Clock inputs Clock Enable input Chip select Command Inputs Bank Address Inputs Input Data Mask Data Input/Output Data Strobe Serial Clock for Presence Detect Presence Detect Address Inputs Serial Presence Detect Data Power Supply Reference voltage Ground Serial EEPROM Power Supply No Connect
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FUNCTIONAL BLOCK DIAGRAM
3
WV3HG64M64EEU-D4
ADVANCED
CS0# DQS0# DQS0 DM0
DM CS#DQS DQS# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ DQ DQ DQ DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQS4# DQS4 DM4
DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ
DQS1# DQS1 DM1
DM CS# DQS DQS# DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ DQ DQ DQ DQ DQ DQ DQ
DQS5# DQS5 DM5
DM CS# DQS DQS# DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ DQ DQ DQ DQ DQ DQ DQ
DQS2# DQS2 DM2
DM CS# DQS DQS# DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ DQ DQ DQ DQ DQ DQ DQ
DQS6# DQS6 DM6
DM CS# DQS DQS# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ DQ DQ DQ DQ DQ DQ DQ
DQS3# DQS3 DM3
DM CS# DQS DQS# DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 3 DQ DQ DQ DQ DQ DQ DQ DQ
DQS7# DQS7 DM7
DM CS# DQS DQS# DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ DQ DQ DQ DQ DQ DQ DQ
100 CK0 CK0# DDR2 SDRAMs DDR2 SDRAMs
SCL
Serial PD
WP A0 A1 A2 SA0 SA1
BA0-BA1 A0-A13 RAS# CAS# WE# CKE0 ODT0
BA0-BA1: DDR2 SDRAMs A0-A13: DDR2 SDRAMs DDR2 SDRAMs RAS#: CAS#: DDR2 SDRAMs WE#: DDR2 SDRAMs CKE0: DDR2 SDRAMs ODT0: DDR2 SDRAMs
SDA
VCCSPD VCC VREF
Serial PD DDR2 SDRAMs DDR2 SDRAMs DDR2 SDRAMs
CK1 CK1#
100 DDR2 SDRAMs DDR2 SDRAMs
NOTE: All resistor value, are 22 ohms 5% unless otherwise specified.
VSS
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ABSOLUTE MAXIMUM RATINGS
Symbol VCC VIN, VOUT TSTG IL Parameter Voltage on VCC pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Input leakage current; Any input 0VWV3HG64M64EEU-D4
ADVANCED
Min -0.5 -0.5 -55 Command/Address, RAS#, CAS#, WE# CS#, CKE CK, CK# DM -80 -40 -20 -5 -5 -16
Max 2.3 2.3 100 80 40 20 5 5 16
Units V V C uA uA uA uA uA uA
IOZ IVREF
Output leakage current; 0VDQ, DQS, DQS#
DC OPERATING CONDITIONS
All voltages referenced to VSS Rating Parameter Supply Voltage I/O Reference Voltage I/O Termination Voltage Symbol VCC VREF VTT Min. 1.7 0.49 x VCC VREF-0.04 Type 1.8 0.50 x VCC VREF Max. 1.9 0.51 x VCC VREF+0.04 Units V V V 1 2 Notes
Notes: 1. VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1percent of the DC value. Peak-to-peak AC noise on VREF may not excedd +/-2 persent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor. 2. VTT in sot applied directly to the device. VTT is a system supply for signal terminaion resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF.
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INPUT/OUTPUT CAPACITANCE
TA = 25C, f = 100MHz Parameter Input Capacitance (A0~A13, BA0~BA1, RAS#, CAS#, WE#) Input Capacitance CKE0, ODT Input Capacitance CS0# Input Capacitance (CK0, CK0#, CK1, CK1#) Input Capacitance (DM0 ~ DM7), (DQS0 ~ DQS7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 (667) CIN5 (533) Input Capacitance (DQ0 ~ DQ63) COUT1 (667) COUT1 (533)
Notes: * AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
WV3HG64M64EEU-D4
ADVANCED
Min 12 12 12 8 6.5 6.5 6.5 6.5
Max 20 20 20 12 7.5 8 7.5 8
Units pF pF pF pF pF pF pF pF
OPERATING TEMPERATURE CONDITION
Parameter Operating temperature Symbol TOPER Rating 0 to 85 Units C Notes 1, 2
Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measuremnet conditions, please refer to JEDED JESD51.2 2. At 0C - 85C, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS Parameter Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Symbol VIH(DC) VIL(DC) Min VREF + 0.125 -0.300 Max VCC + 0.300 VREF - 0.125 Units V V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS Parameter Input High (Logic 1) Voltage DDR2-400 & DDR2-533 Input Low (Logic 1) Voltage DDR2-667 Input Low (Logic 0) Voltage DDR2-400 & DDR2-533 Input Low (Logic 0) Voltage DDR2-667 Symbol VIH(DC) VIH(DC) VIL(DC) VIL(DC) Min VREF + 0.250 VREF + 0.200 Max VREF - 0.250 VREF - 0.200 Units V V V V
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ICC SPECIFICATION
Symbol ICC0* Proposed Conditions
WV3HG64M64EEU-D4
ADVANCED
665 680
534 640
403 640
Units mA
Operating one bank active-precharge; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge; IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address businputs are SWITCHING; Data pattern is same as ICC4W Precharge power-down current; All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputsare STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 Slow PDN Exit MRS(12) = 1
ICC1*
800
760
720
mA
ICC2P**
64
64
64
mA
ICC2Q**
280
240
240
mA
ICC2N**
320 240 96
280 280 96
280 240 96
mA mA mA
ICC3P**
ICC3N**
Active standby current; All banks open; tCK = tCK(ICC), tRC = tRC(ICC, tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W Burst auto refresh current; tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs vre FLOATING; Data bus inputs are FLOATING Normal
440
400
400
mA
ICC4W*
1120
960
880
mA
ICC4R*
1160
1000
880
mA
ICC5**
1200
1120
1120
mA
ICC6** ICC7*
64
64
64
mA
Operating bank interleave read current; All bank interleaVINg reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.
1760
1760
1760
mA
ICC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. Note: *: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode. **: Value calculated reflects all module ranks in this operating condition.
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AC CHARACTERISTICS PARAMETER CL = 5 CL = 4 CL = 3 CK high-level width CK low-level width Half clock period Clock jitter DQ output access time from CK/CK# Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS DQ and DM input hold time relative to DQS DQ and DM input pulse width (for each input) Data hold skew factor DQ...DQS hold, DQS to first DQ to go nonvalid, per access Data valid output window (DVW) DQS input high pulse width DQS input low pulse width DQS output access time from CK/CK# DQS falling edge to CK rising ... setup time DQS falling edge from CK rising ... hold time DQS...DQ skew, DQS to last DQ valid, per group, per access DQS read preamble DQS read postamble DQS write preamble setup time DQS write preamble DQS write postamble Write command to first DQS latching transition
Address and control input pulse width for each input Address and control input setup time Address and control input hold time Address and control input hold time
WV3HG64M64EEU-D4
ADVANCED
AC TIMING PARAMETERS & SPECIFICATIONS
665 SYMBOL tCK (5) tCK (4) tCK (3) tCH tCL tHP tJIT tAC tHZ tLZ tDS tDH tDIPW tQHS tQH tDVW tDQSH tDQSL tDQSCK tDSS tDSH tDQSQ tRPRE tRPST tWPRES tWPRE tWPST tDQSS
tIPW tIS tIH tCCD
534 MAX 8,000 8,000 8,000 0.55 MIN 3,750 5,000 0.45 MAX 8,000 8,000 0.55 MIN 5,000 5,000 0.45
403 MAX 8,000 8,000 0.55 UNIT ps ps ps tCK tCK ps ps ps ps ps ps ps tCK ps ps ns tCK tCK ps tCK tCK ps tCK tCK ps tCK tCK tCK
tCK ps ps tCK
MIN 3,000 3,750 5,000 0.45
0.45 0.55 MIN (tCH, tCL) 250 -450 +450 tAC MAX tAC MIN tAC MAX 100 225 0.35 340 tHP - tQHS tQH - tDQSQ 0.35 0.35 -400 0.2 0.2
0.45 0.55 MIN (tCH, tCL) 250 -500 +500 tAC MAX tAC MIN tAC MAX 100 225 0.35 400 tHP - tQHS tQH - tDQSQ 0.35 0.35 -450 0.2 0.2
0.45 0.55 MIN (tCH, tCL) 250 -600 +600 tAC MAX tAC MIN tAC MAX 150 275 0.35 450 tHP - tQHS tQH - tDQSQ 0.35 0.35 -500 0.2 0.2
Data
+400
+450
+500
Data Strobe
240 0.9 0.4 0 0.35 0.4 WL - 0.25
0.6 200 275 2
300 0.9 0.4 0 0.35 0.4 WL - 0.25
0.6 250 375 2
350 0.9 0.4 0 0.35 0.4 WL - 0.25
0.6 350 475 2
1.1 0.6
1.1 0.6
1.1 0.6
0.6 WL + 0.25
0.6 WL + 0.25
0.6 WL + 0.25
Note: AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. Continued on next page
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AC CHARACTERISTICS PARAMETER
ACTIVE to ACTIVE (same bank) command ACTIVE bank a to ACTIVE bank b command ACTIVE to READ or WRITE delay Four Bank Activate period ACTIVE to PRECHARGE command Internal READ to precharge command delay Write recovery time Auto precharge write recovery + precharge time Internal WRITE to READ command delay PRECHARGE command period PRECHARGE ALL command period LOAD MODE command cycle time CKE low to CK,CK# uncertainty REFRESH to Active of Refresh to Refresh command interfal
WV3HG64M64EEU-D4
ADVANCED
AC TIMING PARAMETERS (cont'd)
665 SYMBOL
tRC tRRD tRCD tFAW tRAS tRTP tWR tDAL tWTR tRP tRPA tMRD tDELAY tRFC tREFI tXSNR tXSRD tISXR tAOND tAON tAOFD tAOF tAONPD tRFC (MIN) + 10 200 tIS 2 tAC (MIN) 2.5 tAC (MIN) tAC (MIN) + 2000 tAC (MIN) + 2000 3 8 2 7 - AL 2 3 2 tAC (MAX) + 1000 2.5 tAC (MAX) + 600 2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1000
534 MAX MIN
60 7.5 15 37.5 45 7.5 15 tWR + tRP 7.5 15 tRP+tCK 2 tIS + tCK + tIH 105
403 MAX MIN
65 7.5 15 37.5 45 7.5 15 tWR + tRP 10 15 tRP+tCK 2 tIS + tCK + tIH 105
MIN
55 7.5 15 37.5 45 7.5 15 tWR + tRP 7.5 15 tRP+tCK 2 tIS + tCK + tIH 105
MAX
UNIT
ns ns ns ns ns ns ns ns ns ns ns tCK ns ns s ns tCK ps
Command and Address
37.5 70,000
37.5 70,000
37.5 70,000
70,000 7.8
70,000 7.8
70,000 7.8
Self Refresh
Average periodic refresh interval Exit self refresh to non-READ command Exit self refresh to READ command Exit self refresh timing reference ODT turn-on delay ODT turn-on ODT turn-off delay ODT turn-off
tRFC (MIN) + 10 200 tIS 2 tAC (MIN) 2.5 tAC (MIN) tAC (MIN) + 2000 tAC (MIN) + 2000 3 8 2 6 - AL 2 3 2 tAC (MAX) + 1000 2.5 tAC (MAX) + 600 2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1000
tRFC (MIN) + 10 200 tIS 2 tAC (MIN) 2.5 tAC (MIN) tAC (MIN) + 2000 tAC (MIN) + 2000 3 8 2 6 - AL 2 3 2 tAC (MAX) + 1000 2.5 tAC (MAX) + 600 2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1000
tCK ps tCK ps ps
ODT
ODT turn-on (power-down mode)
ODT turn-off (power-down mode) ODT to power-down entry latency ODT power-down exit latency Exit active power-down to READ command, MR[bit12=0] Exit active power-down to READ command, MR[bit12=1] A Exit precharge power-down to any non-READ command. CKE minimum high/low time
tAOFPD tANPD tAXPD tXARD tXARDS tXP tCKE
ps tCK tCK tCK tCK tCK tCK
Note: AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
May 2006 Rev. 2
Power-Down
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Clock/Data Rate Frequency 333MHz/667Mb/s 266MHz/533Mb/s 200MHz/400Mb/s
WV3HG64M64EEU-D4
ADVANCED
ORDERING INFORMATION FOR D4
Part Number WV3HG64M64EEU665D4xxG* WV3HG64M64EEU534D4xxG WV3HG64M64EEU403D4xxG
* Consult Factory for availability NOTES: * RoHS product. ("G" = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
CAS Latency 5 4 3
tRCD 5 4 3
tRP 5 4 3
Height** 30.00mm (1.181") TYP 30.00mm (1.181") TYP 30.00mm (1.181") TYP
PACKAGE DIMENSIONS FOR D4
FRONT VIEW
67.75 (2.667) 67.45 (2.656) 3.80 (0.150) MAX
4.10(0.161) (2X) 3.90(0.154)
1.80 (0.071) (2X)
30.15 (1.187) 29.85 (1.175) 20.00 (0.787) TYP
6.00 (0.236) 2.55 (0.100) 1.10 (0.043) 0.90 (0.035) 1.00 (0.039) TYP 0.45 (0.018) TYP 63.60 (2.504) TYP 0.60 (0.024) TYP
2.15 (0.085)
PIN 199
PIN 1
BACK VIEW
PIN 200
47.40 (1.866) TYP
4.2 (0.165) TYP 11.40 (0.449) TYP
PIN 2
** ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
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PART NUMBERING GUIDE
WV3HG64M64EEU-D4
ADVANCED
WV 3 H G 64M 64 E E U xxx D4 x x G
WEDC MEMORY (SDRAM) DDR 2 GOLD DEPTH BUS WIDTH COMPONENT WIDTH x8 1.8V UNBUFFERED SPEED (Mb/s) PACKAGE 200 PIN INDUSTRIAL TEMP OPTION (For commercial leave "blank" for industrial add "I") COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = ROHS COMPLIANT
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Document Title
512MB - 64Mx64 DDR2 SDRAM UNBUFFERED DRAM DIE OPTIONS: * SAMSUNG: C-Die, will move to E-Die Q2'06 * MICRON: U37Y: B-Die
WV3HG64M64EEU-D4
ADVANCED
Revision History Rev #
Rev 0 Rev 1
History
Created 1.0 Updated VCC spec
Release Date
January 2006 Feburary 2006
Status
Advanced Advanced
Rev 2
2.1 Updated AC specs 2.2 Updated ordering information 2.3 Added industrial temp option on part numbering guide 2.4 Added die rev info
May 2006
Advanced
May 2006 Rev. 2
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